(1) Field of the Invention
The present invention relates to a test circuit, a selector, and a semiconductor integrated circuit, and more particularly, to a test circuit that tests a plurality of tri-state devices having their outputs connected to the same node and a selector including the test circuit.
(2) Description of the Related Art
In recent years, semiconductor integrated circuits have been becoming denser and faster year by year, and with this, element circuits included in the semiconductor integrated circuits, which are constituent elements, are strongly required to realize high-speed operations while fulfilling easy fault detection.
An example of basic element circuits is a selector, and selectors that use tri-state devices have been known for years as selectors which operate at high speed. However, it is also known that fault detection is difficult in selectors that use tri-state devices.
Among tri-state devices, the following are considered faults that are difficult to detect by the selector that uses a tri-state device: when the control signal of at least one of the included tri-state devices malfunctions and this causes a fault in which the output of the tri-state device is always in high-impedance state (that is, when a non-selection state occurs); and a fault in which occurs when the output is always in non-high-impedance state (that is, when multiple selection occurs).
As a conventional solution to this problem, a method is known that is described in Japanese Laid-Open Patent Application No. 11-52019. According to this method, by providing the output part of the selector including tri-state devices with the function of pulling up or pulling down the output part at the time of the scan test only, the output is fixed to the logic “1” or “0” even when the control signal malfunctions to cause the non-selection state while minimizing the deterioration in the speed of the selector in the normal operation, so that fault detection can be correctly performed.
Hereinafter, a conventional selector using tri-state devices will be described by use of the drawings.
FIG. 1 shows the structure of the conventional selector shown in Japanese Laid-Open Patent Application No. 11-52019 mentioned above.
The selector 1000 shown in FIG. 1 includes tri-state devices 1001 and 1002 and a transistor 1003.
The tri-state device 1001 outputs the logical value of a data input terminal 1011 to a data output terminal 1040 when a data selection terminal 1021 is active. The output of the tri-state device 1001 is in high-impedance state when the data selection terminal 1021 is non-active. Likewise, the tri-state device 1002 outputs the logical value of a data input terminal 1012 when a data selection terminal 1022 is active. The output of the tri-state device 1002 is in high-impedance state when the data selection terminal 1022 is non-active.
The transistor 1003 is an NMOSFET, and has the function of pulling down the data output terminal 1040 when a scan mode signal terminal 1031 is active. The transistor 1003 is formed by a driving performance that is sufficiently low compared to that of the tri-state devices 1001 and 1002.
With this structure, when at least one of the data selection terminals 1021 and 1022 is faulty and the tri-state devices 1001 and 1002 are both high impedance, the scan mode signal terminal 1031 is active at the time of the scan test, the transistor 1003 pulls down the data output terminal, and the data output terminal 1040 outputs the logical value “0”. Consequently, by the scan test, it can be judged that a fault occurs also when at least one of the data selection terminals 1021 and 1022 are faulty. In the normal operation, since the scan mode signal terminal 1031 is non-active, the adverse effect on the operating speed can be minimized.